/**
 * 1. always
 **/

module alu #(
    parameter   PASS0 = 3'B000,
                PASS1 = 3'B001,
                ADD   = 3'B010,
                AND   = 3'B011,
                XOR   = 3'B100,
                PASSD = 3'B101,
                PASS6 = 3'B110,
                PASS7 = 3'B111
) (
    input [7 : 0] data, accum,
    input [2 : 0] opcode,
    output reg zero,
    output reg [7 : 0] out
);
    always @(accum) begin
        zero = !accum;
    end
    always @(data, accum, opcode) begin
        case (opcode)
            PASS0: out = accum;
            PASS1: out = accum;
            ADD: out = (data + accum);
            AND: out = (data & accum);
            XOR: out = (data ^ accum);
            PASSD: out = data;
            PASS6: out = accum;
            PASS7: out = accum;
            default: out = 8'B0;
        endcase
    end
endmodule